FIG. 1 contains a block diagram of a conventional memory system 10 having a plurality of memory devices M0-Mm, e.g., m=7, on a plurality of memory modules MM0-MMn, 14, 12, connected to a controller 16. The number m of memory devices M0-Mm on each memory module MM0-MMn is determined with respect to the system bus width. For example, if the system bus width is x64 and the memory devices have a x8 DQ bus, each memory module MM0-MMn has eight memory devices M0-M7. Data signal lines DQ0-7, DQ8-15, . . . , DQ56-63 have multi-drop links, such that the memory devices share the data signal lines. The capacitive load of the data lines affects the operation speed of the memory system. For example, 8 SDRAM, 4DDR (double data rate), 2DDR2 and 2DDR3 operational configurations typically may be connected together to respective data signal lines. As the operating speed of such systems increases, it becomes important to reduce capacitive loading of the data signal lines to avoid the degradation of operation speed introduced by the capacitive loading.
The command/address (C/A) signal lines C/A0 and C/A1 have multi-drop links, so that memory devices M0-Mm on the same module MM0-MMn share the same C/A signal line. In general, 8 or 4 memory devices share a single C/A line, depending on the system bus speed. For higher bus speeds, 8 memory devices typically share a common C/A line.
At present, the speed of a C/A line is slower than that of a data DQ line because of the loading effects. For DDR operation, the C/A bus is being operated at single data rate (SDR), half of the DQ speed. For higher speed operation, it will also be important to reduce capacitive loading and stub of the C/A line.
For a high-speed memory system, i.e., a system operating at more than 2 Gbps, a point-to-point (PTP) link, as opposed to a multi-drop link, between memory devices and between the controller and memory devices has been studied to reduce capacitive loading and stub of each signal line to meet high-speed operational requirements. For a high-density memory system supporting the PTP link, a plurality of memory modules are needed to support the memory application such as server or networking, but each memory module comprising the PTP link should have an input/output I/O module tab for each signal line. This causes an increase in the number of tabs, making it difficult to design and produce a suitable memory module. An approach in a high-density memory system supporting PTP without increasing the number of module tabs is to use stacked memories on a single memory module.
If stacked memories mounted on one memory module are adopted, some problems are expected. For example, the thermal management between an upper memory and a lower memory would be a difficult issue to resolve. Also, signal routing between an upper memory and a lower memory would become very complex and difficult to implement, and can lead to an increase in memory package size. Also, it would be difficult to increase the density of the memory system while maintaining the PTP link.